Conventional semiconductor devices had been miniaturized within a planar structure. However, the number of electrons that can be stored in a memory element decreases particularly in NAND flash memory, which has been on the cutting edge of miniaturization, due to its miniaturization. As a result, the reliability of devices had deteriorated due to the physical limit of device characteristics. A solution to this problem is a three-dimensional memory cell structure in which memory elements are arrayed in a vertical direction. This three-dimensional memory cell structure has solved the physical limit of device characteristics, thereby realizing a large capacity of memory elements.
Manufacturers of NAND flash memory are changing from development of conventional semiconductor device miniaturization technology to development of multi-layer technology in three-dimensional memory structure, aiming for further increase in capacity with an increased number of multilayers. In 2016, devices with three-dimensional memory structures of nearly 50 layers have already been put on the market, while there is still a demand for an increase in the number of layers.
On the other hand, inspection objects of processing result of the multi-layer structure of the memory cell include high-aspect hole, foreign matter in the multi-layer structure, pattern covering multiple levels, all of which cannot be inspected by conventional inspection apparatus and measurement apparatus. Since the number of such inspection objects increases, a new inspection method is required.
In particular, end portions of multilayered memory cell arrays are processed to have a staircase shape. These staircase end portions are used for enabling an upper layer to contact each layer of the multilayered memory cells. For this reason, a defect of the staircase patterns is an important matter affecting a non-defective rate of devices.
A conventional inspection of a two-dimensional pattern in a planar structure device uses an image of a pattern, which is generated by a scanning electron microscope (hereinafter referred to as “SEM”) configured to scan a target pattern with an electron beam, detect electrons emitted from the pattern, and convert the electrons into an image.
In order to obtain an image of a pattern formed on a semiconductor wafer, the SEM adjusts the focus of the electron beam using the pattern to be inspected or a pattern in the vicinity of the pattern to be inspected, and then generates the image of the target pattern. A focal depth of the electron beam is several hundreds of nanometers, which is sufficiently large as compared with an asperity of a pattern having a height of at most 100 nm in a planar structure device. Therefore, by adjusting the focus once, it is possible to obtain a clear image of a pattern in the vicinity the target pattern.
In the staircase pattern, a height difference of one step is not more than 100 nm, which is equal to or smaller than the depth of focus of the electron beam. However, a height difference of several tens of steps is several micrometers. As a result, it is impossible to generate a sharp image of the staircase structure with the depth of focus of the electron beam. When images of these three-dimensional layers are to be taken, it is necessary to repeat an adjustment of the focus of the electron beam, a movement to image acquisition coordinates by the XY stage, and image acquisition and inspection for each layer. As a result, an inspection time is remarkably increased.
In the above-described staircase pattern, when a distance between patterns of respective layers is to be inspected, one practical method is to obtain an image of patterns of multiple layers and inspect a relative distance between the patterns on the image. However, when patterns on the multiple layers are to be included in one image, it is impossible to capture a sharp image of patterns whose height difference exceeds the focal depth of the electron beam.
As an existing technology, Japanese laid-open patent document No. 10-149792 discloses a dynamic focus technique. Specifically, this document discloses a scanning electron microscope and a control method thereof in which a focus is changed by an electron beam scanning position when observing an inclined specimen.
However, in order to inspect a semiconductor device, it is necessary to inspect a plurality of positions or a wide region within a plane of a wafer. For this reason, accurate height information in the electron beam scanning range is required for using the above-described known technique.